The reason is that the PNP transistor is open, so the capacitor cannot charge. In practice, prototyped on breadboard, too - except when I try to give the next pulse too soon, the ADSR signal does not "retrigger" to the attack-phase, but seems to hold at the current level of "release". The problem is: In the simulation, everything works fine. When set, the "upper" part is grounded and the voltage divider on the top left sets the reference to which the cap should be discharged, the sustain-level. Two of the inverters used form some kind of Flip-Flop which is set when the capacitor reaches significiant charge and reset when the input pulse goes low. See the attached schematics or the simulation I used to develop this. So I tried to design my own circuit, with reasonable success. A bit more of a problem is: How to generate an ADSR signal? Most of the schematics I found online seemed to be rather complicated and/or used parts I don't have at hand. Well, the VCA right now is nothing more than a voltage divider including an LDR sitting inside a bit of shrink tubing together with an LED. By now I want to make the resulting sounds a bit more interesting by adding a voltage controlled amplifier controlled by an ADSR envelope generator. Long story short, I watched an interesting video on DIY synths/sequencers ( watch?v=FaoJaLmZaL4) and thought I'd give it a try.
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